搜索资源列表
ref-ddr-sdram-verilog.zip
- sdram的verilog的源码实现
ref-ddr-sdram-vhdl
- 用VHDL编写DDR SDRAM Controller的源代码- Compiles DDR SDRAM Controller with VHDL the source code
ref-sdr-sdram-vhdl
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
ref-ddr-sdram-vhdl
- 本程序是DDR SDRAM控制器的VHDL程序,由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
very-good-ok-ref-ddr-sdram-verilog
- Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
ddr
- ISE MIG1.6 生成的DDR SDRAM控制器代码(含TESHBENCH)
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
v4_ddr_sdram_controller
- 利用v4fpga实现sdram ddr控制器设计,很详细的,很实用的资料
完全硬件手册
- RAM(Random Access Memory)随机存取存储器对于系统性能的影响是每个PC用户都非常清楚的,所以很多朋友趁着现在的内存价格很低纷纷扩容了内存,希望借此来得到更高的性能。不过现在市场是多种内存类型并存的,SDRAM、DDR SDRAM、RDRAM等等,如果你使用的还是非常古老的系统,可能还需要EDO DRAM、FP DRAM(块页)等现在不是很常见的内存-RAM (Random Access Memory) random access memory system performa
DDR SDRAM控制器的VHDL代码已经测试
- DDR SDRAM控制器的VHDL代码已经测试
cyclone_ug_ddr_sdram
- ddr——sdram
DDR-SDRAM_IP_core
- DDR-SDRAM接口模块verilog源代码,可用作IP核使用,已在FPGA上验证-DDR-SDRAM interface module verilog source code, can be used as IP cores to use, proven
Altera_DDR_controller_core
- Altera DDR SDRAM控制器完整Verilog代码包,包括Verilog源代码,Doc说明文档,仿真DDR芯片模型,仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, descr iption documents, DDR verilog model and simulation testbench are all included.
mx27ads_x33
- i.mx27开发板的整套详细原理图,包括:DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST,FEC PHY, UART,JTAG等等接口-i.MX27 development board schematic details of the package, including: DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST, FEC PHY, UART, JTAG interface,
SDRAM
- 连接Nios II 和SDRAM的系统设计,DDR SDRAM设计及调试经验总结,MT48LC16M16资料。-failed to translate
DDR SDRAM Design Tutorials
- Altera公司的基于NIOSII设计DDR和DDR2内存的资料,很有帮助的,-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
ddr
- DDR SDRAM 控制器 VHDL代码,可支持32bits数据总线-VHDL code for DDR SDRAM controller, supporting 32bits data bus
DDRSDRAMconclude
- DDR SDRAM技术总结 介绍DDR SDRAM的一些概念和难点 着重讲解主流DDRII的技术 最后结合硬件设计提出一些参考 -DDR SDRAM DDR SDRAM Technical Summary describes some of the concepts and difficult to explain the mainstream DDRII technology focused on the final hardware design combined with some ref
FPGA-SDRAM-control-code
- 该程序是FPGA控制DDR SRAM的控制源代码,使得SDRAM的控制变得简单。-This program is DDR SDRAM control code ,it makes the operation of SDRAM more easy.
DDR-SDRAM
- DDR SDRAM的设计,包括DDR SDRAM控制器,以及Modelsim仿真-The design of DDR SDRAM, DDR SDRAM controller, and Modelsim simulation